An information processing device that performs DMA (Direct Memory Access) transfer between a main memory and a high-speed IO interface, such as SDXC, USB and SATA, using a plurality of channels in parallel has been provided. Such a device prevents reduction of throughput of the DMA transfer.
As a device performing a plurality of data transfer operations in parallel, a disk array device including a plurality of disk devices alternately performing data transfer at regular time intervals is proposed (see Patent Literature 1).
By applying the technology disclosed in Patent Literature 1 to the DMA transfer, three channels CH1, CH2 and CH3 may alternately perform data transfer at regular time intervals as illustrated in FIG. 26, for example. Such a configuration can eliminate the effect of overhead (DMA set processing, DMA termination processing) and prevent the reduction of the throughput of the DMA transfer.
In the DMA transfer to which the technology disclosed in Patent Literature 1 is applied, however, if a size of data to be transferred differs for each opportunity to perform transfer, latency might occur on any of the DMA channels CH1, CH2 and CH3 after the end of a DMA transfer period, thereby causing the reduction of the throughput.
To address this problem, a configuration in which the three DMA channels CH1, CH2 and CH3 each perform continuous DMA transfer operations independently from one another has been provided.
As such a configuration, for example, there is a configuration in which a DMA controller 1030 reads descriptors (transfer control information pieces) D1, D2, D3 and D4 stored in a buffer 6050 for each of the DMA channels CH1, CH2 and CH3 to perform data transfer, as illustrated in FIG. 28.
Here, the buffer 6050 stores, in storage areas thereof, the descriptors D1, D2, D3, D4 and so on in ascending order of an address of each of the storage areas. The descriptors D1, D2, D3, D4 and so on are read in ascending order of an address of each of the storage areas, in accordance with a value of a read pointer RP. For example, when data transfer performed according to the descriptor D3 is completed, the DMA controller 1030 updates the value of the read pointer RP held on the buffer 6050 with an address (x0004) of a storage area in which the descriptor D4 is stored. The DMA controller 1030 then acquires the descriptor D4 stored in the storage area having the address indicated by the read pointer RP, and starts data transfer performed according to the descriptor D4.
A CPU 1000 confirms whether or not all data pieces have been transferred by referencing the value of the read pointer RP held on the buffer 6050. In an example illustrated in FIG. 29, the CPU 1000 recognizes that DMA transfer performed according to the descriptors D1 to D4 is completed at a time Td when the value of the read pointer is updated with the address of the storage area in which the descriptor D4 is stored.